What's the right way to start gate level simulation ?

(cdupaty) Are you working inside ModelSim using a pre-compiled VHDL design and test bench pair (previously compiled in Quartus II)? If you are then I cannot help you because I have had problems using Modelsim as a standalone program, specifically, getting the device libraries loaded in. My previous suggestion was using Quartus II and starting ModelSim-Altera using the Nativelink feature. It is a little easier than I thought/suggested. You don't have to worry about anything behind the 'More EDA Netlist Writer Settings...' button. Just have the 'Run gate-level simulation automatically after compilation' checked. I tried stripping a design file and its test bench file out of a simple project, deleting the project and starting again loading the two files into Quartus and compiling. ModelSim-Altera starts, my test bench script runs and timing delays are present. Inside ModelSim-Altera, in the transcript window I can enter 'Restart' to clear the current simulation (and OK the list of stuff that comes up) and enter 'Run 4 us' or whatever and it resimulates with timing delays. What I can't do is go 'Restart' to clear the current simulation and then go Simulation -> Start Simulation. Sure enough the design and test bench and device libraries are in there (under the different tabs) but it fails. Why? Because it cannot find an instance of my design file (DUT but it could be called anything) in the mydesign_vhd.sdo file. Rightly so because it's not there. I think to use ModelSim in this way you will have to start a project in ModelSim (PE student edition) and compile your files there. But the fun starts when you want to get the device library loaded and I haven't worked out how to do that yet. Perhaps there is a ModelSim guru reading who could help us all.