What's the right way to start gate level simulation ?

I'm a newbie but I start gate-level (timing) simulation as follows: In Quartus, Assignments -> Settings -> Simulation. In the new window I call up ModelSim-Altera as the EDA tool and check the 'Run gate-level simulation automatically after compilation' box. I supply a test bench file and check the 'Compile test bench' radio button. The bit which used to stop me from getting gate-level timing simulations performed is behind the 'More EDA Netlist Writer Settings...' button. Here I have 'Generate third-party EDA tool command script for RTL functional simulation' turned OFF and 'Generate third-party EDA tool command script for gate-level simulation' turned ON (or vice versa if I just want to check functionality). After compilation ModelSim starts, loads all that is needed and a timing waveform appears showing clock-to-output delays of the order of 7ns. The device I always specify in my training exercises is the Cyclone II device in my DE2 development board. Hope this helps. Maybe you can help me. When I use Quartus II v10.1 - given that I have also downloaded and installed ModelSim-Altera 10.1 which is v6.6c - why is ModelSim-Altera 6.5e the version that it calls up in NativeLink?