What is the best way to preserve an FPGA project (with a released build and programming file), so that Timing Analysis can be done later, on that particular build?

You can preserve the logic placement and routing in particular module or block through Design Partition https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-block-based-design.pdf. Normally, we do this when code freeze or it's no longer changed in RTL.