What can cause a clock signal being distributed to a DFF chain to have several delta cycles delay on one DFF?

Hi,

How i fixed it: I deleted that part of the .bdf and redrew it using exactly the same DFF type. Why this worked i don't understand, which is what I'm trying to figure out.

I just compared the .vho files, specifically the port mapping of the clock inputs of the DFFs in question and noticed the following:

inst2: clk => \CLOCK_1600Hz~inputclkctrl_outclk\

inst41: clk => \CLOCK_1600Hz~inputclkctrl_outclk\

inst6: clk => \CLOCK_1600Hz~input_o\

inst44: clk => \CLOCK_1600Hz~inputclkctrl_outclk\

inst11: clk => \CLOCK_1600Hz~inputclkctrl_outclk\

inst45: clk => \CLOCK_1600Hz~inputclkctrl_outclk\

I paired the "equivalent" DFFs to show that the DFF that had a clock signal that had some delta was actually mapped to a different signal than the others. I'll include the parts in the .vho that show where these two signals come from. I don't understand why this happens though.

-- Location: IOIBUF_X0_Y4_N15

\CLOCK_1600Hz~input\ : fiftyfivenm_io_ibuf

-- pragma translate_off

GENERIC MAP (

bus_hold => "false",

listen_to_nsleep_signal => "false",

simulate_z_as => "z")

-- pragma translate_on

PORT MAP (

i => ww_CLOCK_1600Hz,

o => \CLOCK_1600Hz~input_o\);

\CLOCK_1600Hz~inputclkctrl\ : fiftyfivenm_clkctrl

-- pragma translate_off

GENERIC MAP (

clock_type => "global clock",

ena_register_mode => "none")

-- pragma translate_on

PORT MAP (

inclk => \CLOCK_1600Hz~inputclkctrl_INCLK_bus\,

devclrn => ww_devclrn,

devpor => ww_devpor,

outclk => \CLOCK_1600Hz~inputclkctrl_outclk\);

Thanks!

Regards,

Felix