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omar_ibrahim
New Contributor
New Contributorweird behaviour of fitter in quartus SDRAM project
I've been working on SDRAM controller project using verilog using cyclone v 5cefa5f23i7.
The SDRAM have four bank , 3 cas latency and 166 Mhz clock.
I start design with a goal of having lowest po...
sstrell
Super Contributor
Super ContributorNo need to cross-post. I responded to your other post.
omar_ibrahimI post there by wrong
I think this questions is related to quartus prime not programmable device
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