Altera_Forum
Honored Contributor
12 years agoWeak pull-up setting in Q11 & Q12
Hi,
I use EP4CGX50CF23I7 (CYCLONE IV GX) with SPI FLASH (MX25L1635E, VCC = 3,3V). The SPI FLASH output pin SO (SPI_MISO) connect through serial resistor 25[Om] with 2 input port: CPU (Intel Atom, VCCIO SPI Interface = 3,3V) and CYCLONE IV (VCCIO = 3,3V). 3,3V for VCCIO CYCLONE IV, CPU and VCC SPI FLASH power up simultaneously. Input port SPI_MISO in CYCLONE IV was declared but not use in project. In "Devices and Pin Options" -> "Unused Pins" I set option "Reserve all unused pins:" to "As input tri-stated with weak pull-up", compile project in Quartus 11.1 SP2, create jic-file for EPCS64 and programm them. In read data cycle from SPI FLASH the level of logic "1" SPI_MISO signal before serail resistor was ~2V, after serial resistor - 1,8V (very small and pull-up dosn't present!; here in after referred to as "state 1"). After this I set in "Logic Options" (in Assignments Editor) for input pin SPI_MISO - "Weak Pull-Up Resistor" -> "On" and recompile project. I load sof-file (!) to CYCLONE IV using JTAG (ByteBlasterMV) and in read data cycle from SPI FLASH the level of logic "1" SPI_MISO signal before and after serail resistor was become ~3,3V (normal state; here in after referred to as "state 2"). After I create jic-file for EPCS64 and programm them and level of logic "1" SPI_MISO signal returned to state 1 (pull-up dosn't present). After this I copy my project and compile them in Quartus 12.1 and Quartus 12.1 SP1, load sof-file (2 time) to CYCLONE IV using JTAG and received an state 1 (pull-up dosn't present). Programm jic-file (based on sof-file created in Q12) to EPCS64 also returned to state 1. HOWEVER, if I create in Quartus 12.1 jic-file based on sof-file created in Quartus 11.1 and programm them to EPCS64, I returned to state 2 (pull-up present!!!). I have 3 questions: 1. Why I not getting pull-up for input pin in Quartus 12.1 ? 2. Why pull-up is present in sof-file (Q11.1), but not present in jic-file (Q11.1) ? 3. Why pull-up is present in jic-file (Q12.1), based on sof-file created in Q11.1 (in consideration of question 1, 2)? Best regards!