Warning: Removed fan-in from always-disabled I/O buffer

Hi Brad,

Right up front, I'd better say, again, thank you for helping me. I really do appreciate it!

So, let me tell you what I found!

It turns out that the compiler warning that I get (removed fan in from always disabled... etc) when I try to put that register module in my design is being caused by the read enable(not) signal (which is supposed to put the register contents on to the bus). If I replace the register select line that I have the module connected to with one from a different part of the circuit, the compiler error goes away. So, this makes me suspect that there is something wrong with another module that I'm using that routes a signal read(not) on to one of 64 output lines based on an 8 bit address. I'll include the code below and if you see anything suspicious about it please let me know. The crazy part of this whole exercise is that when I model this code using modelsim everything works exactly like I expect it to!

entity registerRdWrSelect is

port

(

nRdIn : in std_logic;

nWrIn : in std_logic;

Addr : in std_logic_vector(7 downto 0);

nRd : out std_logic_vector(63 downto 0);

nWr : out std_logic_vector(63 downto 0)

);

end registerRdWrSelect;

architecture registerRdWrSelect_arch of registerRdWrSelect is

begin -- registerRdWrSelect_arch

readEnableNotSignalDemux:process(Addr, nRdIn)

begin

nRd <= (others => '1');

if nRdIn = '0' then

nRd(to_integer(unsigned(Addr))) <= '0';

end if;

end process;

writeEnableNotSignalDemux:process(Addr, nWrIn)

begin

nWr <= (others => '1');

if nWrIn = '0' then

nWr(to_integer(unsigned(Addr))) <= '0';

end if;

end process;

end registerRdWrSelect_arch;