--- Quote Start ---
But just a point of clarification...there isn't any reason why I shouldn't connect other modules to the same tristate bus right? That's what the tristate is for!
--- Quote End ---
For any particular tristatable pin, be sure all your source files together produce a single tristate buffer. The VHDL code you showed produces its own tristate buffer. If there is another tristate buffer somewhere else for the same device pin, that's a problem. The device does not have an internal tristatable bus, only a single tristate buffer right at the pin. Synthesis might be able to combine multiple tristates in the HDL into a single one in the synthesis result, but it would be much better to write your HDL to describe a single tristate buffer that will map directly to the single one available in the device.
With a single tristate buffer on a particular pin, the input direction on that pin can feed as many things in the design as you want, and as many things as you want can be combined together in logic to feed the output direction. If you have multiple things internal to the FPGA sharing the same tristatable pin, I recommend having the inout VHDL port only in the top-level file.
Honored Contributor
