Honored Contributor
Honored ContributorHi Brad,
Well, you are right on several counts! : ) First, the top level of my design is a schematic and second, there doesn't appear to be anything wrong with the register vhdl code that I submitted for your inspection. A little clarification/history. I am reverse engineering an old design done by one of our engineers that is completely in schematic form ( represented as 7400 series IC's). I've been translating these "circuits" into VHDL and then replacing parts of the schematic with the modules I created. That way I can verify my vhdl modules prior to the time I use them in a new design. When I put that register module back into the original design it works! - no compiler warnings and the circuit behaves as expected. So...apparently there is something wrong with the bus I've got the VHDL module connected to in the new design. But just a point of clarification...there isn't any reason why I shouldn't connect other modules to the same tristate bus right? That's what the tristate is for! Anyway, thank you very much for your help. please check back to this thread 'cause I'll either explain what I found wrong or ask for some more advice! :) Tom
