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Altera_Forum's avatar
Altera_Forum
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12 years ago

warning: output pins without output pin load capacitance assignment

I know this might be very fundamental. However, when I assign a pin to an output, do I need to assign a load capacitance (pf?) to this pin? Or maybe the tool will do it for me? Thanks.
Altera_Forum's avatar
Altera_Forum
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12 years ago

The tool includes the pin capacitance of the package, but not the external device. You can see the difference in the package pin capacitance in the delays calculated for VREF pins versus normal I/O pins.

Quartus does not know what you have connected the FPGA pins to, so its up to you to provide that information. Here's an example ...

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/timequest_quad_spi_flash.zip

Cheers,

Dave