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Hphd's avatar
Hphd
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Warning: Design contains 1 input pin(s) that do not drive logic

Hi guys, I am designing a PUF . I am getting these warnings. IN technology map viewer one of the input Chal[0] is not getting connected, even though it shows a connection in rtl. I have attached a...
  • sstrell's avatar
    sstrell
    5 years ago

    Without seeing the code of arb, this is difficult to follow. But perhaps your instantiation is incorrect. You're using positional port mapping, which makes it very easy to make a mistake in the connections, and you have trig_reg repeated.

    You should instantiate like:

    arb a1 (.<signal in module>(trig_reg), ...);
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Without testing this myself, you're initializing a 16-bit register with a 1 bit value. Perhaps you meant to say:

reg [15:0] Chal1=16'hffff;

or initialize it in the always block:

always @ (posedge clk)
begin
Chal1 <= 16'hffff;
if (trig_signal)
.
.
.

Hphd's avatar
Hphd
Icon for New Contributor rankNew Contributor
5 years ago

Thank you sstrell,

Even this is not making any difference in technology map viewer. Its shows the same warning.

Actually, my logic goes in this way,

1.As posedge of clock pulse, once trig_signal is enabled , i need to make arb module to function .

2. The first loop will have the input as trig_reg and Chal(o). [ Note: I used Chal1 just to verify whether the technology map viewer considers Chal[0] inside the loop]

3. The output of the first loop will be given to sec ond loop along with Chal[1].

The problem which I am facing is LOOP (0) is not getting the Chal(0) signal inside the block so the whole loop will not functiom.Actually , this code is a part of my module.

So, now I need to connect my Chal(0) inside my block. Thank you in advance.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Without seeing the code of arb, this is difficult to follow. But perhaps your instantiation is incorrect. You're using positional port mapping, which makes it very easy to make a mistake in the connections, and you have trig_reg repeated.

    You should instantiate like:

    arb a1 (.<signal in module>(trig_reg), ...);