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Altera_Forum's avatar
Altera_Forum
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14 years ago

Warning: Converted elements in bus name "" using legacy naming rules.

I have a module symbol on my top level block diagram/schematic connected to a few input and output buses. When I compile I always get the the warning "converted elements in bus ... name using legacy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hello

I based a very simple BDF design on an automatically generated project by the Terrassic system builder.

The connections to the LEDR[x] and KEY[0] were not compiled correctly until I followed the setting above.

In Q17 the settings have moved to: Assignments / Settings / Compiler Setting / Advanced Settings (Synthesis) [button] / Block Design Naming { => set this to Quartus II}

Best Regards,

John.