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Altera_Forum's avatar
Altera_Forum
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12 years ago

warning: connected to dangling logic and will be removed

I have the output port width of 12 bits, and the intermediate result is of 14 bit width with the first 3 bits being sign bits (result of 3 addition). I need to remove the first two sign bits (no over...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You can indeed ignore such warnings, provided you are sure they don't come from actual design errors.

Removing them is not a good practice because it makes sense they are kept there: for example, how could Quartus know if the upper 2 bits of your 14bit result have been left unconnected intentionally, or maybe because of a hdl typo ?