Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Wait Statement error in VHDL

I read on bit adder in VHTL in Quartus II 9.1 from this site: http://esd.cs.ucr.edu/labs/adder/add_tst.vhd first according guide I add and compile 1 bit adder,it works correctly ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

First - you need to repost the code with some carrige returns!!

it sounds like you tried to compile a testbench in quartus. You cant do that. You need to run it in a simulator