WADDR, WE, and DATAIN for SYSC_RAM module

Yes, a ROM could solve the problem. I am still learning Verilog language, and the following questions could be very fundamental:

1. What is the correct way to fill values into ROM? Since initial block can not be synthesized, I can't use $readmemh for initialization. Should I simply "assign" a value to the corresponding ROM memory inside the ROM module?

2. In the top-level module that instantiates ROM, will this instantiation of ROM updates its output whenever its input address value changes? I know all the "assign" statements in the top-level module run in this way, but how about an instantiation of an submodule ?