VQM and arbitrary assignments?

Hello,

I would like to push arbitrary assignments into Quartus from a VQM file, just as one can do from Verilog or VHDL sources. c.f. http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf (http://www.altera.com/literature/hb/qts/qts_qii5v1.pdf), pages 9-66 through 9-69.

Unfortunately, Quartus seems to ignore any // synthesis altera_attribute="..." comments in VQM files. Does anyone know a way to force this to work?

I realize there are generally other ways to get around this issue, but project requirements dictate that I can only deliver a .vqm, and it needs to include any assignments that I need.

Neil