ContributorvJTAG Timing Diagrams
Whereabouts can I find some example timing diagrams for data transmission from PC into vJTAG on an FPGA?
I am trying to make sense of what this command does with my logic analyzer but I cannot see the data in the diagram. Even if I *think* can see the data, the TCK signal doesn't seem to correspond to the bits on the TDI signal.
device_virtual_dr_shift -instance_index 0 -length 32 -dr_value 6
So I expect to see a 32 bit transmission that looks like this:
01100000 00000000 00000000 00000000
or
00000000 0000000000000000 00000110
Is the white blip in the below trace the 0110 bits? Why does tck not show 2 cycles within that period if this is the case?
Surely there are some example timing diagrams I can refer to for example data transmission? I can't find any in the Virtual JTAG Intel FPGA IP Core User Guide - at least I cannot find a good example which is clear. I found the DR Shift Waveform but this shows a tidy TCK signal in Modelsim.
Is my logic analyzer not showing TCK correctly??
