VIRTUAL PIN
Hi All,
Is it possible to assign a VIRTUAL Pin to a signal inside of the hierarchies or does it MUST be assigned to a port of the higher hierarchy?
Let's say I have a hierarchy named h1, which is a sub-hierarchy of the top hierarchy h0.
The h1 hierarchy has a signal named sig. Can I assign it to a VIRTUAL Pin without connecting it to a signal in the topper hierarchy h0?
Thanks!
You can use virtual pins only for I/O elements in lower-level design entities that become nodes after you import the entity to the top-level design; for example, when compiling a partial design. In the top-level design, you connect these virtual pins to an internal node of another module.
Reference:
https://www.intel.com/content/www/us/en/docs/programmable/683641/22-3/defining-virtual-pins.html
How about you try to use the Preserve for debug feature to preserve the node for debug?
Reference: https://www.youtube.com/watch?v=sEKc2ut42gU
Best Regards,
Richard Tan