Vhdl

Hello there, this code did not work, so I created a new 4-bit counter and text environment for it but I can not display the signal on 4 7- segment displays ????

architecture beh of johnson_counter is
signal opt: std_logic_vector( 3 downto 0 );
begin
process( clk, rst )
begin
if( rst = '1' ) then
     opt <= "0000";
elsif( rising_edge( clk ) ) then
opt <=( not opt( 0 ) ) & opt( 3 downto 1 );
end if;
end process;
op <= opt;
end beh;
 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity johnson_counter_tb is
end johnson_counter_tb;
architecture Behavioral of johnson_counter_tb is
component johnson_counter is
port( clk: in std_logic;
rst: in std_logic;
op: out std_logic_vector( 3 downto 0 ) );
end component;
signal clk_tb, rst_tb: std_logic:= '1';
signal op_tb: std_logic_vector( 3 downto 0 );
constant clk_period: time:= 10 ns;
begin
DUT: johnson_counter port map( clk_tb, rst_tb, op_tb );
clk_process: process
begin
clk_tb <= not( clk_tb );
wait for clk_period / 2;
end process;
main_process: process
begin
wait for 10 ns;
rst_tb <= '0';
wait for 100 ns;
end process;
end Behavioral;