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That works but I don't understand what is really different. Can you explain?
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There are two ways to set logic priority:
explicit and default
explicit
if count = 10 then
count <= 0;
else
count <= count + 1;
end if;
default (conditional)
count <= count + 1;
if count = 10 then
count <= 0;
end if;
In vhdl process the last statement overwrites so if this last statement is conditional that is ok.
if it is not conditional like your code then it implies unconditional update and compiler optimises off the previous assignment
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Also I have to make the hold time to be at least 8 clock cycles. Is there a document telling that?
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What is this hold time?
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