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Altera_Forum
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11 years ago

VHDL writing in memory

Hi, I have a hardware design running on a Cyclone IV FPGA and a software part running on a Nios II cpu on the very same FPGA. Both are sharing a dual port FPGA memory. I want the hardware part to ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The difference is because a signal in VHDL takes the last value assigned to it. In your origional code, it is reset inside the the "if hold = 10 then" branch, but this is overridden with hold <= hold + 1, hence it is never reset to 0.