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Yes you are right. I tried it too.
In general my problem is to be able to create one solid process per logic entity with complex combinational logic that could also be exported out of the process as asynchronous signals to be used for other processes. In order to achieve that I suppose I have to use variables that get assigned outside the clocked if (but also read but not assigned inside the clocked if) and when I need to export them I can assign the variables-to-be-exported to signals but outside the clocked if.
Another question is that maybe inside the clocked process I need to make a variable assignment. Is it possible to split the clocked if in two (so have two if(rising edge)) inside the same process and in between make asynchronous variable assignments?
process(clk)
variable t1 : std_logic;
variable t2 : std_logic;
begin
t1 := A and B;
if rising_edge(clk) then
Yb <= t1;
end if;
Y <= t1 XOR Yb;
t2 := A or B;
if rising_edge(clk) then
Yc <= t2 OR Y;
end if;
end process;
Is this mixture possible?
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Yes, but the two
'if rising_edge' constructs will be mapped to the same clock.
In fact you can write it also as:
process(clk,A,B,Yb)
variable t1 : std_logic;
variable t2 : std_logic;
begin
t1 := A and B;
Y <= t1 XOR Yb;
t2 := A or B;
if rising_edge(clk) then
Yb <= t1;
Yc <= t2 OR Y;
end if;
end process;
Note that I added Yb to the sensitivity list (because Y depends on it)
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