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Honored ContributorVHDL: Transport delay fails to work properly (in WVF simulation)
I currently have some VHDL code which was written with the intended purpose of simulating waveform "A", and, via transport delay, simulating waveform "SIG" 25ns after the simulation of "A". However, ...
Altera_ForumHonored Contributor
Honored ContributorIf you want delays to be synthesized you will need to use registers and maybe timers. As KAZ said, delays are not synthesizable.
