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Altera_Forum
Honored Contributor
10 years agoVHDL: Transport delay fails to work properly (in WVF simulation)
I currently have some VHDL code which was written with the intended purpose of simulating waveform "A", and, via transport delay, simulating waveform "SIG" 25ns after the simulation of "A". However, ...
Altera_Forum
Honored Contributor
10 years agoyou need modelsim to apply delay, synthesis tools ignore delays.