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Altera_Forum
Honored Contributor
Honored ContributorVHDL Traffic Light - How to make signals viewable in simulation?
Hi there, relatively new to VHDL. At the end of this description I will post my VHDL code and Test Bench. When I simulate the code, the timing seems to be off, I want it to wait 15 clock cycles...
Altera_ForumHonored Contributor
Honored Contributoruse the following command in transcript window
add wave Traffic_Light_Sim/uut/* * indicates that all the signals from the uut will be displayed. Also you can add individual signals by replacing * with the signal name
