VHDL Traffic Light - How to make signals viewable in simulation?

Update: Now the timing works just how I want it, with the 15 and 3 clock cycles per change of state, and I made it more efficient.

If someone could still tell me how to bring out internal signal in the simulation that would be appreciated, thank you.

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 05/24/2016 10:20:40 AM

-- Design Name:

-- Module Name: Traffic_Light_VHDL - Behavioral

-- Project Name:

-- Target Devices:

-- Tool Versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;

use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Traffic_Light_VHDL is

Port (

Reset : in std_logic;

clk : in std_logic;

MG : out STD_LOGIC;

MY : out STD_LOGIC;

MR : out STD_LOGIC;

SG : out STD_LOGIC;

SY : out STD_LOGIC;

SR : out STD_LOGIC

);

end Traffic_Light_VHDL;

architecture Behavioral of Traffic_Light_VHDL is

type state_type is (st0, st1, st2, st3);

--signal PS, NS : state_type;

signal state : state_type;

signal Count : std_logic_vector(3 downto 0);

begin

process(clk, Reset)

begin

if (Reset = '1') then

state <= st0;

Count <= "0000";

elsif (rising_edge(clk)) then

case state is

when st0 =>

if (Count < "1111") then

Count <= Count + 1;

else

state <= st1;

Count <= "0000";

end if;

when st1 =>

if (Count < "0011") then

Count <= Count + 1;

else

state <= st2;

Count <= "0000";

end if;

when st2 =>

if (Count < "1111") then

Count <= Count + 1;

else

state <= st3;

Count <= "0000";

end if;

when st3 =>

if (Count < "0011") then

Count <= Count + 1;

else

state <= st0;

Count <= "0000";

end if;

when others =>

state <= st0;

end case;

end if;

end process;

process(state)

begin

case state is

when st0 =>

MG <= '1';

SR <= '1';

MY <= '0';

SY <= '0';

MR <= '0';

SG <= '0';

when st1 =>

MG <= '0';

SR <= '1';

MY <= '1';

SY <= '0';

MR <= '0';

SG <= '0';

when st2 =>

MG <= '0';

SR <= '0';

MY <= '0';

SY <= '0';

MR <= '1';

SG <= '1';

when st3 =>

MG <= '0';

SR <= '0';

MY <= '0';

SY <= '1';

MR <= '1';

SG <= '0';

when others =>

MG <= '1';

SR <= '1';

MY <= '0';

SY <= '0';

MR <= '0';

SG <= '0';

end case;

end process;

end Behavioral;