VHDL test bench

I don't know how to write test bench coding and i don't know how to see the output.I am writing a simple programme of and gate below:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mrinalnt is

Port ( a : in STD_LOGIC;

b : out STD_LOGIC);

end mrinalnt;

architecture Behavioral of mrinalnt is

begin

b<= not a;

end Behavioral;

Now for test bench the following code is,It is not right,please help....

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY mrinaltst IS

END mrinaltst;

ARCHITECTURE behavior OF mrinaltst IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mrinalnt

PORT(

a : IN std_logic;

b : OUT std_logic

);

END COMPONENT;

--Inputs

signal a : std_logic := '0';

--Outputs

signal b : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mrinalnt PORT MAP (

a => a,

b => b

);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

constant clk_period := 1ns;

clk_process :process

begin

clk <= '0';

wait for 15ns;

clk <= '1';

wait for 15ns;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100ms.

wait for 100ms;

wait for <clock>_period*10;

-- insert stimulus here

wait;

end process;

END;

I don't know what to write in stimulus process,how to declare signal etc....