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Altera_Forum
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14 years ago

VHDL State Machine: Bad State Transitions

Hi, I'm really hoping someone can help me as I'm at my wits end. I am running into a scenario where my state machine is transitioning into an invalid state. As far as I can tell, all of my paths betw...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Using FT2232 in asynchronous mode with 24 MHz clock frequency does not solve the problem addressed in post# 2 to# 4. Synchroniszation is still required as long as FTDI internal and FPGA clock ar unrelated.