VHDL State Machine: Bad State Transitions

change your clk to 24Mhz and use this (LMK if it helps):

-- ft2232d_fifo generation

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity ft2232d_fifo is

port (

clkin : in std_logic; -- 24 MHZ clock from oscillator

resetn : in std_logic; -- global reset to reset everything

usbtxen : in std_logic; -- TX FIFO empty (low means data can go into FIFO)

usbrxfn : in std_logic; -- RX FIFO full (low means data can be read from FIFO)

readfifodata : in std_logic; -- Read Enable

writefifo : in std_logic; -- Write Enable

usbrdn : out std_logic; -- strobe low-then-high to get data from FIFO

usbwr : out std_logic; -- strobe high-then-low to write data into FIFO

usbd : inout std_logic_vector(7 downto 0); -- bi-directional data bus to FIFO chip

data_read : out std_logic_vector(7 downto 0); -- bi-directional data bus to FIFO chip

data_write : in std_logic_vector(7 downto 0) -- bi-directional data bus to FIFO chip

);

end ft2232d_fifo;

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architecture rtl of ft2232d_fifo is

type USB_STATE_TYPE is (USBIDLE,USBGETBYTE,USBSAVEBYTE,

USBRDDN,USBPUTBYTE,USBWOUT,

USBWHLD);

--signal USBState : std_logic_vector(4 downto 0);

--signal USBIDLE : std_logic_vector(4 downto 0) := "00000";

--signal USBGETBYTE : std_logic_vector(4 downto 0) := "00001";

--signal USBSAVEBYTE : std_logic_vector(4 downto 0) := "10001";

--signal USBRDDN : std_logic_vector(4 downto 0) := "01000";

--signal USBPUTBYTE : std_logic_vector(4 downto 0) := "00010";

--signal USBWOUT : std_logic_vector(4 downto 0) := "00110";

--signal USBWHLD : std_logic_vector(4 downto 0) := "01100";

signal USBState : USB_STATE_TYPE;

signal iswrite : std_logic;

signal usbdone : std_logic;

begin

--usbrdn <= NOT USBState(0);

--usbwr <= USBState(1);

--iswrite <= USBState(2);

--usbdone <= USBState(3);

usb_rx_tx: process (resetn,clkin)

begin

if (resetn = '0') then

USBState <= USBIDLE;

usbrdn <= '1';

usbwr <= '0';

iswrite <= '0';

usbdone <= '0';

data_read <= (others => '0');

elsif (rising_edge(clkin)) then

case USBState is

when USBIDLE =>

usbrdn <= '1';

usbwr <= '0';

iswrite <= '0';

usbdone <= '0';

if(readfifodata = '1' AND usbrxfn = '0') then

USBState <= USBGETBYTE;

elsif(writefifo = '1' AND usbtxen = '0') then

USBState <= USBPUTBYTE;

else

USBState <= USBIDLE;

end if;

when USBGETBYTE =>

usbwr <= '0';

iswrite <= '0';

usbdone <= '0';

usbrdn <= '0';

USBState <= USBSAVEBYTE;

when USBSAVEBYTE =>

usbwr <= '0';

iswrite <= '0';

usbdone <= '0';

usbrdn <= '0';

if(readfifodata = '1')then

data_read <= usbd;

end if;

USBState <= USBRDDN;

when USBRDDN =>

usbrdn <= '1';

usbwr <= '0';

iswrite <= '0';

usbdone <= '1';

if(readfifodata = '0' AND writefifo = '0')then

USBState <= USBIDLE;

end if;

when USBPUTBYTE =>

usbrdn <= '1';

usbwr <= '1';

iswrite <= '0';

usbdone <= '0';

USBState <= USBWOUT;

when USBWOUT =>

usbrdn <= '1';

usbwr <= '1';

iswrite <= '1';

usbdone <= '0';

USBState <= USBWHLD;

when USBWHLD =>

usbrdn <= '1';

usbwr <= '0';

iswrite <= '1';

usbdone <= '1';

if(readfifodata = '0' AND writefifo = '0')then

USBState <= USBIDLE;

end if;

end case;

end if;

end process usb_rx_tx;

usbd <= data_write when (iswrite) = '1' else "ZZZZZZZZ";

end rtl;

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