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Altera_Forum
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14 years ago

VHDL State Machine: Bad State Transitions

Hi, I'm really hoping someone can help me as I'm at my wits end. I am running into a scenario where my state machine is transitioning into an invalid state. As far as I can tell, all of my paths betw...
Altera_Forum's avatar
Altera_Forum
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14 years ago

If the incoming signals are asynchrnous, I suggest you synchronise them to the "main_clk" before trying to use them. Without doing that, you will be violating setup and hold times, and any signals that read them may become meta-stable.