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Altera_Forum's avatar
Altera_Forum
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14 years ago

VHDL Simulation Timing Errors

Hi all, I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down: It is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

First of all - this is an altera forum - ISim is a Xilinx Tool.

Secondly, without your code (or a simplified demo that I can run) there is no way I can recreate your problem, so at the moment it just appears to be a problem for you to debug yourself. I have no idea where you are causing the error (because it will be an error in the code, that I cannot see)