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Altera_Forum
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14 years ago

VHDL Simulation Timing Errors

Hi all, I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down: It is a...
Altera_Forum's avatar
Altera_Forum
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14 years ago

The 'p' and 'U' values are incorrect, for some reason it outputs early, 'U' is Unknown, you can see that it outputs at 3 ns with an Unknown Value (which should not occur) and then 1 ns later updates to the correct value. Those lines should be outputting at 5ns after instead of 3 / 4 ns like they are. I am using ISim 0.61xd.