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Altera_Forum
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14 years ago

VHDL Simulation Timing Errors

Hi all, I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down: It is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

ya, the package code is over 2000 lines but I can throw together a detailed example on it.