VHDL Simulation Timing Errors

sub nano logic structures, I am just working on a method of simulation and verification for these logic structures of this system type. I have used a clocking scheme prior to this and have had the exact same results. I have been keeping synthesizable constructs to be able to gather rough information from the synthesis tool, that is why I have been using xc_map, xc_rloc, and xc_uset, hoping to allow from optimal synthesis past what I can but this is pre-synthesis simulation and I am getting these errors.