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Altera_Forum
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14 years ago

VHDL Simulation Timing Errors

Hi all, I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down: It is a...
Altera_Forum's avatar
Altera_Forum
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14 years ago

But that then begs the question - what are you actually modelling? If your final system is going to be nothing like this, as getting exact nanosecond scale delays from an FPGA is going to be near impossible, why not just make it a synchronous design?