VHDL Simulation Timing Errors

This question makes be wonder what you've actually done. Have you created a custom type with a custom resolution function? are you using the after and transport keywords? Remember that these kinds of things are ingored by the synthesisor because they do not relate exactly to real logic. any tri-state drivers are converted to muxes and delays are ignored. Can you post your "custom" logic? I can only assume quartus has converted it all to memory based look-up tables.

Your custom types and things will equate to FPAG LUTs and registers at the end of the day. The synthesisor will then minimise your logic as much as it can.

Remember that timing delays cannot be garanteed in a design because of varying routing delays. The best way to get everything to work properly is to use a clock, or you will have to hand place pretty much every single LUT.

So can you post your custom type and resolution function?