VHDL signal assignment with the OTHERS keyword

Try this for size:

below your signal declarations add:

constant period_shift : unsigned (timecounter'length - period'length - 1 downto 0) := (others => '0');

this creates a vector of all zeroes whose length is determined by the length of timecounter and period- i.e. suppose you change periodto be 10 bits - this line stays the same.

Then in your process put:

nexttime <= timecounter + (period & periodshift);

Again if you change the range of period or timecounter then everything rolls through automatically and you don't have to update any other code.

Regarding mmTuschi's question:

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Does outputsignal <= ((23 downto 16) => inputsignal(7 downto 0), others => '0'); work ?

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I think it works for individual bits but not for ranges like this - unless one of the more recent VHDL standards have changed this and I haven't noticed.

On a slightly different note, most people I know prefer numeric_std over std_logic_unsigned or signed - the latter two aren't actually IEEE packages but Mentor / Synopsis packages that have cheekily been compiled into the IEEE library. numeric_std is an IEEE standard.

Hope this helps.