VHDL signal assignment with the OTHERS keyword

Thank you, it clarified a part of what I was thinking.

Another take on this.

using ieee.std_logic_unsigned but could change to numeric_std if I needed.

I have inputs from another module:

signal timecounter: unsigned(31 downto 0);

signal period: unsigned(7 downto 0);

And a signal that is used for a schedule off the main timer.

signal nexttime: unsigned(31 downto 0;

process(clk)
  if(clk'EVENT and clk = '1') then
     if(timecounter = nexttime) then
        -- do stuff
        -- do more stuff
        -- This is where the problem begins, need to cast the period(7 downto 0) to (31 downto 0) somehow and shift it left by 24 bits.
        nexttime <= timecounter + period shifted left by 24 bits
     end if;
  end if;
end process;

One solution I can think of is to do an assignment as above with a variable in the process, and then use the variable in the add operation. I'm just wondering if there is a prettier way.