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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL signal assignment with the OTHERS keyword

I'm not sure I'm posting this in the right place but I want to assign an unsigned or std_logic_vector to the same type of a larger size. Input is 8 bits wide, outputsignal is 32 bits wide and I wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Does outputsignal <= ((23 downto 16) => inputsignal(7 downto 0), others => '0'); work ?

I have similar assignments in one of my projects : 


ES <= (  
         0 => ...,
         1 => 
         2 => 
         3 => 
         4 => 
         5 => 
         6 => 
         7 => 
         others => '-'
         );

others are assigned to "don't care"

It seems working.