VHDL signal assignment with the OTHERS keyword

Hi Frank

Daixiwen is correct - this works inside a process - sorry I should have said that. Basically in a process, the last assignment is the one that takes effect. The result of this is that you can make a default assignment right at the beginning of the process and then effect changes to the default with or without conditions.

e.g.:

process (set_to_ones, do_something_else)
begin
    output <= (others <= '0');
    if set_to_ones = '1' then
        output <= (others => '1'(;
    elsif do_something_else = '1' then
        output <= "1ZX0HL-U";
    end if;
end process;

Basically this means that if none of the if branches execute, then the (others => '0') assignment will be output; if one of the other signals is high then the default (others => '0') assignment is overwritten and has no effect.

Going back to baldur's query, if I write:

process
begin
     outputsignal <= (others => '0');
     outputsignal (23 downto 16) <= inputsignal;
end process;

then the (others => '0') gets assigned to all bits, but some bits have this overridden by the next statement. Bits 23 downto 0 never in effect see the '0' assigment.