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Altera_Forum
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17 years ago

VHDL signal assignment with the OTHERS keyword

I'm not sure I'm posting this in the right place but I want to assign an unsigned or std_logic_vector to the same type of a larger size. Input is 8 bits wide, outputsignal is 32 bits wide and I wa...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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Sorry, batfink, just short question,

the behaviour would be right regarding its original funtion?

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Yes, but only if written inside a process. In that case the second line will override the assignments done in the first one.

Outside a process these two lines will generate a multiple drivers error from the synthesizer as they are concurrent.