Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

VHDL signal assignment with the OTHERS keyword

I'm not sure I'm posting this in the right place but I want to assign an unsigned or std_logic_vector to the same type of a larger size. Input is 8 bits wide, outputsignal is 32 bits wide and I wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Or you could write:

outputsignal <= (others => '0');

outputsignal (23 downto 16) <= inputsignal;