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Honored Contributor
Honored ContributorVHDL sequential vs concurrent statement
Hi, I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragment...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The code you posted was very trivial. But you shouldnt care about the signal assignments in simulation or synthesis. If you get a missmatch between simulation and synthesised hardware, there is a problem - usually a problem of poorly written code. Ie. never use shared variables! --- Quote End --- Thank you..
