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Altera_Forum's avatar
Altera_Forum
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10 years ago

VHDL sequential vs concurrent statement

Hi, I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragment...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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The code you posted was very trivial. But you shouldnt care about the signal assignments in simulation or synthesis. If you get a missmatch between simulation and synthesised hardware, there is a problem - usually a problem of poorly written code.

Ie. never use shared variables!

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Thank you..