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Thank you, Tricky..very much appreciated. Sorry to restart after so long, was badly stuck somewhere else..
So can I conclude that if we do multiple assignments to different signal (within a single process block) then the difference between sequential signal assignment and concurrent signal assignment matter for simulation purposes only. There is no difference for synthesizeable code (e.g. the code I posted in first post)?
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The code you posted was very trivial. But you shouldnt care about the signal assignments in simulation or synthesis. If you get a missmatch between simulation and synthesised hardware, there is a problem - usually a problem of poorly written code.
Ie. never use shared variables!
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