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Altera_Forum
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10 years ago

VHDL sequential vs concurrent statement

Hi, I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragment...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Thank you, Tricky..very much appreciated. Sorry to restart after so long, was badly stuck somewhere else..

So can I conclude that if we do multiple assignments to different signal (within a single process block) then the difference between sequential signal assignment and concurrent signal assignment matter for simulation purposes only. There is no difference for synthesizeable code (e.g. the code I posted in first post)?