VHDL sequential vs concurrent statement

What could blow novice's brain up it is very weak description for differences between dataflow and behaviour paradigms.

----

But if it allowed to say "each concurrent assignment involve indirectly process operator with sensitivy list where all signals that used on right of assignment expression" ?

----

And then if we have fully synchronous design we can put all action in one very big process(clock-signal) (sounds like joke)

And for novice it is worth to ask such questions : "How to describe synchronus design using dataflow paradigm? is it possible?", "Has dataflow paradigm any limitation?"