VHDL sequential vs concurrent statement

Thank you both Tricky and alex96 for your valuable comments. I am trying to figure out the differences.

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Firstly, a single line vhdl statement actually infers a process with all the signals on the rhs in the sensitivity list. Si you actually have 3 processes in parallel.

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Yes, this is what happens when we use concurrent statements.

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Secondly, signals are only updated when a process suspends. When a signal assignment is made, it is only scheduled to be updated at the end of the current delta cycle, so all three signals are updated at the same time.

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So can I conclude there is no such thing as sequential signal assignment in VHDL?

In most books and online tutorials, e.g. in RTL Hardware Design by Prof Chu, it is written "The syntax of a sequential signal assignment is identical to that of the simple concurrent signal assignment of Chapter 4 except that the former is inside a process"- Page 100. In book, he discussed about assignment to same signal multiple times in a process which results in only last assignment take effect. I can understand that. But what is missing in that book and in all of the online tutorials I have seen so far is example/discussion of sequential signal assignment to multiple signals. It seems there is no difference between sequential signal assignment and concurrent signal assignment in that case, but then why we have sequential signal assignment in the first place and if it is (I mean sequential assignment) executed same as concurrent assignment then why name it different?

@alex96...thank you for the link..