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P.S. @Tricky: the result will be the same but will be time for simulation equal too?
and one exception:
process(all) requires VHDL-2008 support. it seems so. if i wrong let me know
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Yes, that is a VHDL 2008 construct, but Quartus and all simulators I know support it.
As for simulation time? are you refering to simulation time or simulator speed?
Sim time is identical for both, as all signals are scheduled to update at the end of any delta where their inputs change. so when in1 or in2 change, out will change 2 deltas later.
As for simulator speed - I would assume they would have decent compiler optimisation to catch these kind of mergable bits of code. You'd have to test you simulator to find out.
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