Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

VHDL sequential vs concurrent statement

Hi, I am bit confused over sequential vs concurrent statements in VHDL. In almost all books, it is mentioned as process body will contain sequential statements. Consider following code fragment...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

to @sawaak:

You have to learn about dataflow/behaviour/structur concept . Also learn difference between VHDL code for synthesis and for simulation.

by the way this link might be helpful for you http://esd.cs.ucr.edu/labs/tutorial/vhdl_page.html (http://esd.cs.ucr.edu/labs/tutorial/vhdl_page.html)

i think it is old one but feel free to surf the web.

P.S. @Tricky: the result will be the same but will be time for simulation equal too?

and one exception: process(all) requires VHDL-2008 support. it seems so. if i wrong let me know