VHDL sequential vs concurrent statement

This is where you need to understand vhdl mechanics. Firstly, a single line vhdl statement actually infers a process with all the signals on the rhs in the sensitivity list. Si you actually have 3 processes in parallel. Secondly, signals are only updated when a process suspends. When a signal assignment is made, it is only scheduled to be updated at the end of the current delta cycle, so all three signals are updated at the same time.